(1) Field of the Invention
This invention relates generally to DRAM memories and relates more particularly to methods to reduce power consumption during read/write operation from/to DRAM memory cells.
(2) Description of the Prior Art
The importance of optimizing the power consumption of memory systems is growing rapidly. Many new applications are more and more data-intensive. For ASICs and embedded systems memory systems can contribute up to 90% of the power consumption of the total system.
In prior art in order to reduce energy consumption pulsed word lines have been introduced to isolate memory cells from the bit lines after sensing thus preventing the cells from changing the bit line voltage further. The generation of word line pulses is very critical because in case they are too short, the sense amplifier operation may fail and if the word pulses are too long too much power will be consumed.
There are known patents dealing with precharging of DRAMs.
U.S. Pat. No. 6,147,916 (to Ogura) teaches a semiconductor memory device, such as a DRAM, including a memory cell array and pairs of bit lines connected to the memory cells in the array. A precharge circuit is connected the bit line pairs and selectively provides the bit line pairs with a reference power supply voltage when the memory cells are being accessed and a precharge voltage when the memory cells are not being accessed. A correction circuit adjusts the precharge voltage in accordance with a difference between the precharge voltage and the reference power supply voltage so that the precharge voltage becomes substantially equal to the reference power supply voltage. A retention mode determination circuit detects when the memory device is in a retention mode (powered down state) and prevents access to the memory cells at this time.
U.S. Pat. No. 6,556,482 (to Shimoyama et al.) discloses a semiconductor memory device including an address register circuit and data register circuit that can store a write address and write data from one write operation and output the stored write address and write data during a subsequent write operation. In a dynamic random access memory (DRAM) embodiment, a precharge and/or refresh operation may follow the writing of previously stored write data. Such an arrangement may reduce and/or eliminate a read after write timing requirement (TWR), which can improve the operating speed of the semiconductor memory device.
U.S. Pat. No. 5,892,722 (to Jang et al.) introduces a column selection circuit, in which a layout area is minimized by reducing the number of data bus lines and sensing speed characteristic is improved by reducing sensing time of a bit line. In a memory for transmitting data stored in a memory cell to a main sensing amplifier through a bit line and a bit bar line and storing the data output from the main sensing amplifier in the memory cell through the bit line and the bit bar line, the column selection circuit includes an equalizer for equalizing the bit line and the bit bar line, a bit line sensing amplifier for compensating signal voltage levels of the bit line and the bit bar line as a word line is selected, first and second enable signal output portions for outputting enable signals to operate the bit line sensing amplifier, a data bus line and a data bus bar line for transmitting the data transmitted to the bit line and the bit bar line from the memory cell to the main sensing amplifier, and transmitting the data output from the main sensing amplifier to the bit line and the bit bar line, a data transmission portion for selectively transmitting the data of the data bus line and data bus bar line and the data of the bit line and bit bar line between the respective lines in response to a column selection signal, a control signal for reading and a write enable signal, and a precharge level adjusting portion for adjusting precharge level of the data bus line and the data bus bar line.